The present invention relates to a semiconductor device, and a method of manufacturing the same. A tensile stress film is formed on an N channel MIS type transistor, and a compressive stress film is formed on a P channel MIS type transistor, whereby it is easy to contrive enhancement of the current drive performance of both the transistors.
Enhancement of the performance of MIS type transistors has been conducted by miniaturization of a gate or the like. However, it is presumed that enhancing the performance by miniaturization has its limitation, and search for a break-through technology superior to the miniaturization technology has come to be vigorously made at present. One of the candidates for the break-through technology is a technology in which the stress in a channel portion is varied by utilizing the stress in a silicon nitride (SiN) inter-layer film, so as to enhance the current drive performance.
It is known that the current drive performance of an N channel MIS type transistor is enhanced by forming a silicon nitride (SiN) film having a tensile stress. It is known, on the other hand, that the current drive performance is degraded when a silicon nitride (SiN) film having a compressive stress is formed. In addition, it is known that the current drive performance of a P channel MIS type transistor is enhanced by forming a silicon nitride (SiN) film having a compressive stress. On the other hand, the current drive performance is known to be degraded when a silicon nitride (SiN) film having a tensile stress is formed. Thus, both of the compressive stress film and the tensile stress film are in a trade-off relationship as to the P channel type transistor and the N channel type transistor.
Accordingly, in order to simultaneously enhance the current drive performance of an N channel MIS type transistor and the current drive performance of a P channel MIS type transistor, it may be necessary to produce a structure in which a silicon nitride (SiN) film having a tensile stress is formed on the N channel MIS type transistor, while a silicon nitride (SiN) film having a compressive stress is formed on the P channel MIS type transistor.
Here, one example of the method of producing the above-mentioned structure in the related art (see, for example, Re-published PCT Patent (A1) WO 02/043151) will be described below, referring to FIGS. 5A to 5H.
As shown in FIG. 5A, a silicon substrate 111 is formed with an N channel MIS type transistor (hereinafter referred to as NMIS transistor) 121 and a P channel MIS type transistor (hereinafter referred to as PMIS transistor) 131. Thereafter, a first inter-layer film 141 composed of a silicon nitride (SiN) film having a tensile stress is formed by a thermal CVD process or a plasma CVD process. In this instance, the stress possessed by the first inter-layer film 141 is regulated by the film forming conditions such as the film forming temperature, the pressure of the film forming atmosphere, etc. It is known that, when a inter-layer film having a stress is thus formed, the stress in a channel portion of each MIS type transistor is influenced by the stress and the thickness of the inter-layer film and the structure of the MIS type transistor (see, for example, Re-published PCT Patent (A1) WO 02/043151).
Next, as shown in FIG. 5B, a silicon oxide (SiO2) film 142 is formed on the first inter-layer film 141 having the tensile stress. This film 142 serves as a stopper film for preventing the first inter-layer film 141 having the tensile stress from being etched when a second inter-layer film having a compressive stress on the NMIS transistor 121 will later be removed by dry etching.
Subsequently, as shown in FIG. 5C, the NMIS transistor 121 is covered with a resist pattern 151 by a lithography process.
Next, as shown in FIG. 5D, using the resist pattern 151, the silicon oxide film 142 on the PMIS transistor 131 is removed by dry etching. Thereafter, the resist pattern 151 is removed. The removal of the resist pattern 151 is carried out, for example, by an asher process.
Subsequently, as shown in FIG. 5E, using the silicon oxide film 142 as a hard mask, the first inter-layer film 141 having the tensile stress on the PMIS transistor 131 is removed by dry etching.
Next, as shown in FIG. 5F, the second inter-layer film 143 having a compressive stress is formed so as to cover the whole surface on the side of the PMIS transistor 131, by a thermal CVD process or a plasma CVD process. The second inter-layer film 143 is composed, for example, of a silicon nitride (SiN) film having a compressive stress. In this instance, the stress possessed by the second inter-layer film 143 is controlled by the film forming conditions such as the film forming temperature, the pressure of the film forming atmosphere, etc.
Subsequently, as shown in FIG. 5G, the PMIS transistor 131 is covered with a resist pattern 152 by a lithography process. In this case, for enhancing the adhesion of the resist to the under film, a silicon oxide (SiO2) film (not shown) having a thickness of several nanometers may be formed on the second inter-layer film 143 having the compressive stress, or the surface of the second inter-layer film 143 may be oxidized by an ashing treatment.
Next, as shown in FIG. 5H, using the resist pattern 152 [see FIG. 5G], the second inter-layer film 143 having the compressive stress on the NMIS transistor 121 is removed by dry etching.